Testing implementation suitable for built-in self-repair...

Details Testing implementation suitable for built-in self-repair... Testing implementation suitable for built-in self-repair...

2007-02-27

2007-02-27

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

09872582

ABSTRACT:
A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially output the digital data to be received by the output register. Each one of the plurality of shift registers includes a feedback path for enabling the digital data output by a corresponding one of the plurality of shift registers to be input back into the corresponding shift register in a same sequence as the digital data is output from the corresponding shift register.

REFERENCES:
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patent: 5033048 (1991-07-01), Pierce et al.
patent: 5231314 (1993-07-01), Andrews
patent: 5815512 (1998-09-01), Osawa et al.
patent: 6065134 (2000-05-01), Bair et al.
patent: 6701476 (2004-03-01), Pouya et al.
Abramovici et al. in “Digital Systems Testing and Testable Design” IEEE Press 1990.

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