Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-12-12
2001-07-10
Nguyen, Hoa T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06260163
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to a method of testing electronic devices. More particularly, it relates to testing high I/O integrated circuits on a low I/O tester
BACKGROUND OF THE INVENTION
Electronic devices, such as semiconductor chips are usually tested before being shipped to customers. This testing verifies that the chip design meets the function it was designed for and checks for any manufacturing defects. The tests include patterns of 1's and 0's to test the internal circuits and logic on the chip and to test the chip's inputs/outputs (I/O). I/O can be (receivers), outputs (drivers), and combined input/outputs that provide both the receiver and the driver function connected to one chip pad.
As described in a paper, “The Advantages of Boundary-Scan Testing, by S. L. Dingle et al.” published in the Proceedings of the 9th IEEE Test Symposium, Atlantic City, N.J., Apr. 16-18, 1991, boundary scan has been used to reduce the number of I/O pins requiring simultaneous contact for testing the logic of chips designed according to level sensitive scan design (LSSD) rules. In an LSSD design, all latches are part of a scannable chain. Boundary scan adds the requirement that each driver and receiver must have an associated latch that is also part of a scannable chain. Therefore, with boundary scan and LSSD, it is possible to directly control and observe the state of all drivers, receivers, and latches on chip while contacting only scan pins (including boundary scan pins), clocks, and LSSD control pins. In this manner, a low-pin-count tester can effectively test all of a chip's area except the chip circuitry outside the boundary scan latches. The circuits not tested by the LSSD/boundary-scan test can be parametrically tested, either by multiplexing on the product/tester interface board or by adding low-cost parametric pins to the tester. Thus, although the internal circuits and logic can usually be tested through a relatively small number of the chip's pads, each chip I/O must still be contacted separately to accomplish its test.
On semiconductor chips having many I/O, testers have been used that have one tester I/O channel for each chip I/O. However, this approach has become increasingly costly, especially as the number of chip I/O exceeds 512. Multiplexing two or more chip I/O to one tester channel with relays on an interface board between the tester and the chip have avoided the expense of high I/O testers. But the relays have raised the size, cost and complexity of interface boards and their control software. In addition, series resistance introduced by the relays have degraded the ability to accurately test chip performance.
Thus, a better solution for testing chips having a large number of I/Os is needed that eliminates the need for relays and reduces the cost and complexity of interface boards while providing that low I/O testers can still be used, and this solution is provided by the present invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a low cost and high performance way to test high I/O count integrated circuits with a low I/O count tester.
It is a feature of the present invention that the integrated circuit is designed to have control over the on/off state of the drivers.
It is a feature of the present invention that tester front end hardware shorts groups of I/Os to each tester channel.
It is an advantage of the present invention that significantly decreased cost of testing high I/O chips is achieved while improving the accuracy of testing.
These and other objects, features, and advantages of the invention are accomplished by a method of testing an electronic assembly, the method comprising the steps of:
(a) providing an electronic assembly having m I/Os, said electronic assembly having enabling switches to control the activation state of said I/Os;
(b) providing a tester having n I/O channels, n being less than m, said tester having front end hardware;
(c) shorting a plurality of said m I/Os in said tester front end hardware;
(d) using the enabling switches of step (a) and activating a first I/O of the plurality of shorted I/Os on the chip while leaving others of said plurality inactive; and
(e) providing a stimulation to test a chip function through said first I/O.
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S. L. Dingle et al., “The Advantages of Boundary-Scan Testing,” Apr. 16-18, 1991, 9th Annual IEEE Test Symposium, Atlantic City, New Jersey.
Lacroix Luke D.
Noel Leo A.
International Business Machines - Corporation
Leas James M.
Nguyen Hoa T.
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