Testing hard-wired IP interface signals using a soft scan chain

Details Testing hard-wired IP interface signals using a soft scan chain Testing hard-wired IP interface signals using a soft scan chain

2003-12-30

2008-10-14

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S725000, C714S724000, C714S727000, C714S729000, C714S742000, C714S030000, C714S734000, C326S038000, C326S040000, C326S041000

Reexamination Certificate

active

07437635

ABSTRACT:
A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of the reconfigurable device. Additionally, the set of boundary scan registers only exists when a testing configuration is loaded into the reconfigurable device. When testing is complete, the testing configuration is erased and the functional blocks may implement other operations. Thus, the set of boundary scan registers consumes no additional chip area. Furthermore, as the set of boundary scan registers disappears after testing, a functional path enabling normal operation modes is unnecessary. Therefore, manually created functional test data is not needed. Instead, ATPG software can create test data from hardware descriptions of the IP core and the set of boundary scan registers.

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