Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-10-23
2007-10-23
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S726000
Reexamination Certificate
active
11194540
ABSTRACT:
A method is provided for testing RAM blocks embedded in an integrated circuit. The method provides a scan circuit embedded in an integrated circuit. The scan circuit includes a RAM block, a plurality of first flip-flops each sending a read address to the RAM block, a plurality of second flip-flops each sending a write address to the RAM block, a plurality of third flip-flops each sending an enable signal to the RAM block, a plurality of fourth flip-flops, and a multiplexer receiving an output from the RAM block, the first, second, third and fourth flip-flops being connected in series. An internal scan test is performed by loading serial data into the first, second, third and fourth flip-flops.
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Product Data Sheet, “Two Port SRAIM 32 Words 32 Bits per word”, Virtual Silicon Technology, Inc., Sunnyvale, CA, 2002.
Manelli Denison & Selter PLLC
Ton David
Turkevich Leon R.
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