Testing content addressable static memories

Details Testing content addressable static memories Testing content addressable static memories

1999-08-11

2002-12-17

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

06496950

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
FIELD OF THE INVENTION
The present invention relates generally to methods for testing memory devices. More particularly, the present invention relates to methods for detecting faults in dual port and single port content addressable static memories.
BACKGROUND OF THE INVENTION
CAM Architecture
Fast, efficient testing is an important step in manufacturing memory chips, and the price paid for recent advances in semiconductor technology has been a lengthier and more complicated testing process. A common feature of some memory devices is the capability to quickly search for patterns stored among groups of memory cells. These types of memory devices are called content addressable memories (CAM's). Just like other memory devices, a CAM is arranged as an array of memory cells, each cell being capable of storing an electric charge. These charges can be manipulated to store and recall data through the use of special control circuitry in the memory. Each memory cell can store one of two values, depending on whether or not the cell holds a charge. The values 1 and 0 are typically used to represent the charged and uncharged states, respectively, although the reverse may be true. Because the cells can hold either of two possible values (i.e., a 1 or a 0), the cell data values are known as binary digits, or “bits.”
In addition to a mechanism for storing data, content addressable memories cells each include a comparison circuit having a “compare” input signal and a “match” output signal. Typically, a group of cells share the same compare signal, while each cell outputs its own match signal. When a binary value (i.e., a 1 or 0) drives the compare input, each memory cell having the same value as the compare input activates (or “asserts”) its match signal. This single-cell matching mechanism is useful for quickly finding data patterns among a plurality of cells in the memory device.
FIG. 1
illustrates a representative CAM 150, comprising an array of memory cells
100
-
103
and
110
-
113
. As shown in
FIG. 1
, the cells are organized into 2 rows and 4 columns, although the cells may be organized into any number of rows and columns. Cells
100
-
103
represent the four columns of row
0
, and cells
110
-
113
represent the four columns of row
1
. Each cell includes a storage logic “S” and a comparison logic “C.” The storage logic S holds the charge that identifies the data value. Each row of cells couples to a “word line” signal that activates the storage logic S of each cell for reading and writing data. The cells
100
-
103
on row
0
, for instance, couple to word line WL
0
, and the cells
110
-
113
on row
1
couple to word line WL
1
.
The storage logic of each cell also couples to a “bit line” signal, which is shared with other cells in the same column. An inverted bit line also couples to each cell in the same column, carrying a 0 value if the main bit line has a 1 value or a 1 value if the main bit line carries a 0 value. Cells
100
and
110
, for example, representing the first column of the array
150
, couple to main bit line BL
0
and to inverted bit line BL
0
′. Similarly the cells
101
and
111
in the second column couple to bit lines BL
1
and BL
1
′, the cells
102
and
112
in the third column couple to bit line BL
2
and BL
2
′, and the cells
103
and
113
in the final column couple to bit lines BL
3
and BL
3
′. To read data from a particular cell, the word line coupled to that cell is asserted, causing that cell to dump data from the storage logic S onto the bit lines. To write a data value into a particular cell, the data value is placed onto the bit lines coupled to the cell. Activating the cell's word line then causes the cell to store the data value from the bit lines into the storage logic S.
The comparison logic C of each cell couples to the cell's storage logic S and to a pair of compare signals. Each column of cells shares a common pair of compare signals, including a main compare line and an inverted compare line. Cells
100
and
110
, for example, couple to main compare line CL
0
and inverted compare line CL
0
′, and cells
101
and
111
share the main compare line CL
1
and the inverted compare line CL
1
′. Similarly, the storage logic of cells
102
and
112
receive main compare line CL
2
and inverted compare line CL
2
′, while cells
103
and
113
receive main compare line CL
3
and inverted compare line CL
3
′. In each cell, the comparison logic C generates a match signal based on the value stored in the cell and on the value of the compare signals. As illustrated in
FIG. 1
, the match signals on row
0
are ML
00
(cell
100
), ML
01
(cell
101
), ML
02
(cell
102
), and ML
03
(cell
103
). Similarly, the match signals on row
1
are ML
10
(cell
110
), ML
11
(cell
111
), ML
12
(cell
112
), and ML
13
(cell
113
). The architecture of CAM
150
is known as a dual port configuration, since the main bit lines are separate from the main compare lines. In a type of configuration known as single port, one signal line functions as both the main bit line and the main compare line, and another signal line functions as the inverted bit line and inverted compare line for each cell.
Memory cells usually are accessed in groups called “words.” Memory words comprise at least two contiguous cells on the same row and share a common word line. For each word, an AND gate
125
may couple together match lines belonging to the cells in that word, to form a unified representation of the match line values. The memory array
150
in
FIG. 1
, for instance, is constructed using four-bit words, including a first word consisting of the cells
100
-
103
on row
0
, and a second word consisting of the cells
110
-
113
on row
1
. An AND gate
125
A receives the match lines ML
00
, ML
01
, ML
02
, and ML
03
belonging to cells
100
-
103
. Similarly, an AND gate
125
B receives the match lines ML
10
, ML
11
, ML
12
, and ML
13
belonging to cells
110
-
113
. Each AND gate
125
generates a word match signal that is asserted if each of the received match lines is asserted. AND gate
125
A, for example, asserts the word match 0 signal if each of the match signals ML
00
, ML
01
, ML
02
, and ML
03
is asserted, and the AND gate
125
B asserts the word match 1 signal if each of the match lines ML
10
, ML
11
, ML
12
, and ML
13
is asserted.
Using the compare and match lines, the CAM array
150
is capable of indicating which data words contain a certain pattern. First, the CAM
150
receives the data pattern through the compare lines. The compare lines carry the pattern to be matched, and the inverted compare lines carry the complement of the pattern to be matched. If the value of a cell matches the value on the associated main compare line, then that cell asserts its match line. If the value of a cell matches the value on the inverted compare line, however, then that cell deasserts its match line. If all of the match lines in the same word are asserted, indicating that the pattern exactly matches the sequence of bits in the data word, then the AND gate belonging to that word asserts the match word signal. An encoder or other circuit may be used to generate a code, based on which word match signals are asserted, that identifies the locations (or “addresses”) of those words in the memory. Thus, any pattern in the memory array can be quickly located by driving the compare lines with the values in the pattern.
FIG. 2A
illustrates an exemplary dual port CAM cell, including the storage logic and comparison logic. The storage logic comprises a pair of cross coupled inverters
200
and
204
and two pass transistors
208
and
212
. The output terminal of inverter
200
represents the cell value D, and the output terminal of inverter
204
represents the inverse of the cell value, D′. The gates of the pass transistors
208
and
212
couple to the word line (WL), so that the pass transistors
208
and
212
become activated

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