Testing circuit split between tiers of through silicon...

Details Testing circuit split between tiers of through silicon... Testing circuit split between tiers of through silicon...

2011-03-08

2011-03-08

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S537000, C257S048000, C257S700000, C257S713000, C257S777000

Reexamination Certificate

active

07904770

ABSTRACT:
A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.

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International Search Report-PCT/US2009/056059, International Search Authority-European Patent Office Feb. 9, 2010.
Written Opinion-PCT/US2009/056059, International Search Authority-European Patent Office Feb. 9, 2010

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