Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-05-29
2007-05-29
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000
Reexamination Certificate
active
10949192
ABSTRACT:
A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
REFERENCES:
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 6138257 (2000-10-01), Wada et al.
patent: 6233182 (2001-05-01), Satou et al.
patent: 6340823 (2002-01-01), Kitade
patent: 6445627 (2002-09-01), Nakahara et al.
patent: 6480869 (2002-11-01), Fujioka
patent: 6567941 (2003-05-01), Turnquist et al.
patent: 6631344 (2003-10-01), Kapur et al.
patent: 6727723 (2004-04-01), Shimizu et al.
patent: WO98/47152 (1998-10-01), None
Aoki Hideyuki
Kikuchi Shuji
Kobayashi Fumie
Suzuki Iwao
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Renesas Technology Corp & Hitachi ULSI Systems Co., Ltd.
Ton David
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