Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-05-08
2007-05-08
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S715000, C714S718000, C714S736000, C714S738000, C714S744000, C714S025000, C714S745000, C365S201000, C702S108000
Reexamination Certificate
active
11097982
ABSTRACT:
A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the testing apparatus includes a timing generating unit for generating sequentially a plurality of timing signals having different timings during the setup testing or the hold testing on the basis of a fist offset value given before starting the setup testing or the hold testing; a pattern generating unit for generating the clock signal and the data signal; a pattern formatting unit for shifting the phase of the data signal with respect to the clock signal sequentially according to the timing signals sequentially generated and providing the DUT with the clock signal and the phase-shifted data signal sequentially; and a determining module for acquiring a setup time or a hold time of the DUT on the basis of storage data which are the data signals stored by the DUT.
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International Search Report for Internation Application No. PCT/JP03/12462 mailed on Jan. 20, 2004, 2 pages.
Doi Masaru
Sato Shin-ya
Tanaka Kouichi
Advantest Corporation
Lamarre Guy
Osha & Liang LLP
Trimmings John P
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