Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-11-16
2000-12-12
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714733, 714 30, G01R 3128
Patent
active
061612057
ABSTRACT:
A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.
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Cady Albert De
Lin Samuel
Micro)n Technology, Inc.
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