Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-28
2002-03-12
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S030000
Reexamination Certificate
active
06357025
ABSTRACT:
TECHNICAL FIELD
This invention relates to systems for testing integrated circuit chips. This invention also relates to methods for conducting such tests.
BACKGROUND OF THE INVENTION
Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as “die”. The “die” are also commonly referred to as “chips” and comprise the finished circuitry components of, for example, processors and memory circuits. Common types of memory circuits include DRAM and SRAM chips.
After a semiconductor wafer has been fabricated, not all chips provided on the wafer prove operable, resulting in less than 100% yield. Accordingly, individual die must be tested for functionality. The typical test procedure for DRAM or SRAM circuitry is to first etch the upper protective passivation layer to expose desired bonding pads on the individual die. Thereafter, the wafer is subjected to test probing whereby the individual die are tested for satisfactory operation. Inoperable die are typically marked by an ink mark. After testing, the wafer is severed between individual chips. The operable, non-marked die are collected.
The operable individual die are then assembled in final packages of either ceramic or plastic. After packaging, the die are loaded into burn-in boards which comprise printed circuit boards having individual sockets. The burn-in boards are placed into a bum-in oven, and the parts are subjected to burn-in testing during which the die are operated for a period of time at different temperature cycles, including high temperatures. The die are stressed to accelerate their lives in an effort to identify the weak die which are likely to fail. Manufacturers predict early failures, known as “infant mortalities”, to occur within a predetermined period of time of the burn-in cycle. Burn-in testing is conducted for a period of time sufficient to reveal these infant mortalities. For example, if infant mortalities are expected to occur within forty-eight hours of burn-in testing, the burn-in tests can be completed within this time period. In this manner, semiconductor wafer manufacturers can effectively test the quality of their chips in a reasonable time frame prior to shipping the chips to consumers.
According to the above testing procedures, the die are subjected to a preliminary wafer-level test before severing, and a burn-in test after severing and packaging of the individual dies Each of these two separate tests require some physical connection with testing apparatus. During the wafer-level test (before severing individual die), portions of the wafer passivation are removed to expose test bonding pads, and then test probes are employed to directly contact these test bonding pads. During the burn-in testing (after severing the individual die), each individual chip must be inserted into burn-in boards for the test.
This invention provides a system and method for preliminary wafer-level testing and burn-in testing without physically contacting the semiconductor wafer or individual die.
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De'cady Albert
Lin Samuel
Micro)n Technology, Inc.
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