Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-08-01
2006-08-01
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
07085973
ABSTRACT:
All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.
REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4855669 (1989-08-01), Mahoney
patent: 5072418 (1991-12-01), Boutaud et al.
patent: 5142625 (1992-08-01), Nakai
patent: RE34363 (1993-08-01), Freeman
patent: 5274570 (1993-12-01), Izumi et al.
patent: 5311114 (1994-05-01), Sambamurthy et al.
patent: 5339262 (1994-08-01), Rostoker et al.
patent: 5347181 (1994-09-01), Ashby et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5457410 (1995-10-01), Ting
patent: 5473267 (1995-12-01), Stansfield
patent: 5500943 (1996-03-01), Ho et al.
patent: 5504738 (1996-04-01), Sambamurthy et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5543640 (1996-08-01), Sutherland et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5552722 (1996-09-01), Kean
patent: 5574930 (1996-11-01), Halverson, Jr. et al.
patent: 5574942 (1996-11-01), Colwell et al.
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5600845 (1997-02-01), Gilson
patent: 5640527 (1997-06-01), Pecone et al.
patent: 5652904 (1997-07-01), Trimberger
patent: 5671355 (1997-09-01), Collins
patent: 5705938 (1998-01-01), Kean
patent: 5732250 (1998-03-01), Bates et al.
patent: 5737631 (1998-04-01), Trimberger
patent: 5740404 (1998-04-01), Baji
patent: 5742179 (1998-04-01), Sasaki
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5748979 (1998-05-01), Trimberger
patent: 5752035 (1998-05-01), Trimberger
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5774409 (1998-06-01), Yamazaki et al.
patent: 5809517 (1998-09-01), Shimura
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5874834 (1999-02-01), New
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5892961 (1999-04-01), Trimberger
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 5933023 (1999-08-01), Young
patent: 5940342 (1999-08-01), Yamazaki et al.
patent: 5970254 (1999-10-01), Cooke et al.
patent: 5974498 (1999-10-01), Hopkins
patent: 6011407 (2000-01-01), New
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6026481 (2000-02-01), New et al.
patent: 6031391 (2000-02-01), Couts-Martin et al.
patent: 6096091 (2000-08-01), Hartmann
patent: 6154051 (2000-11-01), Nguyen et al.
patent: 6163166 (2000-12-01), Bielby et al.
patent: 6172990 (2001-01-01), Deb et al.
patent: 6178541 (2001-01-01), Joly et al.
patent: 6181163 (2001-01-01), Agrawal et al.
patent: 6191998 (2001-02-01), Reddy et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6242945 (2001-06-01), New
patent: 6272451 (2001-08-01), Mason et al.
patent: 6279045 (2001-08-01), Muthujumaraswathy et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6301696 (2001-10-01), Lien et al.
patent: 6343207 (2002-01-01), Hessel et al.
patent: 6353331 (2002-03-01), Shimanek
patent: 6356987 (2002-03-01), Aulas
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6434735 (2002-08-01), Watkins
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6507942 (2003-01-01), Calderone et al.
patent: 6510548 (2003-01-01), Squires
patent: 6518787 (2003-02-01), Allegrucci et al.
patent: 6519753 (2003-02-01), Ang
patent: 6522167 (2003-02-01), Ansari et al.
patent: 6532572 (2003-03-01), Tetelbaum
patent: 6539508 (2003-03-01), Patrie et al.
patent: 6541991 (2003-04-01), Horncheck et al.
patent: 6542969 (2003-04-01), Sato
patent: 6587995 (2003-07-01), Duboc et al.
patent: 6588006 (2003-07-01), Watkins
patent: 6601227 (2003-07-01), Trimberger
patent: 6604228 (2003-08-01), Patel et al.
patent: 6611951 (2003-08-01), Tetelbaum et al.
patent: 2001/0049813 (2001-12-01), Chan et al.
patent: 2002/0023197 (2002-02-01), Miura et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 0315272 (1989-10-01), None
patent: 0 905 906 (1999-03-01), None
patent: 1 235 351 (2002-08-01), None
patent: WO 93 25968 (1993-12-01), None
Sayfe Kiaei et al., “VLSI Design of Dynamically Reconfigurable Array Processor-DRAP,” IEEE, Feb. 1989, pp. 2484-2488, V3.6, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Vason P. Srini, “Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC,” IEEE, May 1991, pp. 309-314, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
G. Maki et al., “A Reconfigurable Data Path Processor,” IEEE, Aug. 1991, pp. 18-4.1 to 18-4.4, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jacob Davidson, “FPGA Implementation of Reconfigurable Microprocessor,” IEEE, Mar. 1993, pp. 3.2.1-3.2.4, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al., “Beyond Superscaler Using FPGA's,” IEEE, Apr. 1993, pp. 486-490, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
P.C. French et al., “A Self-Reconfiguring Processor,”;IEEE, Jul. 1993, pp. 50-59, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al., “Spyder: A reconfigurable VLIW Processor Using FPGA's,” IEEE, Jul. 1993, pp. 17-24, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Michael J. Wirthlin et al., “The Nano Processor: A Low Resource Reconfigurable Processor,” IEEE, Feb. 1994, pp. 23-30, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
William S. Carter, “The Future of Programmable Logic and its Impact on Digital System Design,” Apr. 1994, IEEE, pp. 10-16, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Andre' DeHon, “DPGA-Coupled Microprocessor: Commodity ICs for the Early 21st Century,”IEEE, Feb. 1994, pp. 31-39, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Osama T. Albaharna, “Area & Time Limitations of FPGA-Based Virtual Hardware,” IEEE, Apr. 1994, pp. 184-189, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx, Inc., “The Programmable Logic Data Book,” 1994, Revised 1995, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc., “The Programmable Logic Data Book,” 1994, Revised 1995, pp. 2-109 to 2-117, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc., “The Programmable Logic Data Book,” 1994, Revised 1995, pp. 2-9 to 2-18; 2-187 to 2-199, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc., “The Programmable Logic Data Book,”1994, Revised 1995, pp. 2-107 to 2-108, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Christian Iseli et al., “AC++ Compiler for FPGA Custom Execution Units Synthesis,” 1995, pp. 173-179, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
International Business Machines, “PowerPC 405 Embedded Processor Core User Manual,” 1996, 5TH Ed., pp. 1-1 to X-16, International Business Machines, 1580 Rout 52, Bldg. 504, Hopewell Junction, NY 12533-6531.
Yamin Li et al., “AIZUP-A Pipelined Processor Design & Implementation on Xilinx FPGA Chip,” IEEE, Sep. 1996, pp. 98-106, 98-106, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Ralph D. Wittig et al., Onechip: An FPGA Processor with Reconfigurable Logic, Apr. 17, 1996, pp. 126-135, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx, Inc., “The Programmable Logic Data Book,
Chan H. C.
Kerveros James C.
Lamarre Guy
Ward Thomas A.
Xilinx , Inc.
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