Tester system having multiple instruction memories

Details Tester system having multiple instruction memories Tester system having multiple instruction memories

2006-05-02

2006-05-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

07039841

ABSTRACT:
An apparatus for testing an integrated circuit includes a sequence control logic unit having an output channel connectable to an input pin of a device under test, a first memory to store a first instruction set comprising instructions executable by the sequence control logic unit, and a second memory to store a second instruction set comprising instructions executable by the sequence control logic unit, wherein at least one of the first memory and the second memory comprises a memory accessible in a non-sequential fashion.

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patent: 6286120 (2001-09-01), Reichert et al.
patent: 6826721 (2004-11-01), Williamson et al.
“Reducing Test Application Time in High-level Test Generation” by Ravi et al. International Test Conference Proceedings, 200 Publication Date: Oct. 3-5, 2000 pp.: 829-838 INSPEC Accession No.:6859172.
International Search Report, International Application No.: PCT/US03/14726, Dec. 22, 2003, pp. 1-2.

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