Tester-compatible timing translation system and method using tim

Details Tester-compatible timing translation system and method using tim Tester-compatible timing translation system and method using tim

1998-07-29

2000-05-23

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060676523

ABSTRACT:
A system comprises translation software to convert non-tester-compatible simulation results into tester-compatible test patterns in a ATE system. An intermediate output of the system includes tester-compatible input stimulus for use in re-simulating a circuit design. The resulting simulation output data is tester-compatible, by definition, and can be used to generate tester-compatible test patterns that correspond to a verified simulation of the circuit design. Partnered time sets and signal state data are used in translation between tester-compatible and non-tester-compatible timings.

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