Tester channel count reduction using observe logic and...

Details Tester channel count reduction using observe logic and... Tester channel count reduction using observe logic and...

2006-08-15

2006-08-15

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000, C714S738000, C714S046000

Reexamination Certificate

active

07093174

ABSTRACT:
Test logic supports the testing of an electronic circuit, where the number of ports of the electronic circuit exceeds the number of available tester IO channels. In some examples, the test logic utilizes observe logic in order to analyze the output ports that are masked so that the number of tester IO channels need not be expanded. Digital data from an electronic circuit is compacted by processing the data with a signature compactor to determine a signature corresponding to the output data. A comparator may compare the determined signature with the correct signature to provide a “go
o-go” indication to a process through a processor channel. Providing test coverage using a signature averts the necessity of having additional tester IO channels to cover the associated section of the electronic circuit. Additionally, a pattern generator may be supported by the test logic to provide digital activity for the electronic circuit.

REFERENCES:
patent: 5694401 (1997-12-01), Gibson
patent: 6789221 (2004-09-01), Hapke
patent: 6829740 (2004-12-01), Rajski et al.
patent: 2003/0210069 (2003-11-01), Kikuchi et al.

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