Test systems and methods with compensation techniques

Details Test systems and methods with compensation techniques Test systems and methods with compensation techniques

2007-04-10

2007-04-10

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S700000, C714S055000

Reexamination Certificate

active

10841019

ABSTRACT:
The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.

REFERENCES:
patent: 6268753 (2001-07-01), Sandusky
patent: 6522162 (2003-02-01), Griffin et al.
Toshiyuki Okayasu et al., “CMOS Circuit Technology for Precise GHz Timing Generator,”IEEE: ITC International Test Conference, Paper 31.2, pp. 894-902 (2002).
Mark R. Barber, “Fundamental Timing Problems in Testing MOS VLSI on Modern ATE,”IEEE Design&Test, pp. 90-97 (Aug. 1984).
James A. Gasbarro et al., “Integrated Pin Electronics for VLSI Functional Testers,”IEEE Journal of Solid-State Circuits, vol. 24(2), pp. 331-337 (Apr. 1989).
James A. Gasbarro et al., “A Single-Chip, Functional Tester for VLSI Circuits,”IEEE International Solid State Circuits Conference, pp. 84-86 (Feb. 1990).
A.T. Sivaram, “Split Timing Mode (STM)—Answer to Dual Frequency Domain Testing,”IEEE ITC International Test Conference, Paper 6.1, pp. 140-147 (2001).
Robert Hägglund et al., “Tuning and Compensation of Temperature Effects in Analog Integrated Filters,” Department of Electrical Engineering, Linköping University, no date.

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