Test system for integrated circuits using a single memory for bo

Details Test system for integrated circuits using a single memory for bo Test system for integrated circuits using a single memory for bo

1997-09-16

2000-04-11

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 30, G01R 3128

Patent

active

06049901&

ABSTRACT:
A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.

REFERENCES:
patent: 4947357 (1990-08-01), Stewart et al.
patent: 5260947 (1993-11-01), Posse
patent: 5530706 (1996-06-01), Josephson et al.
patent: 5606568 (1997-02-01), Sudweeks
patent: 5648973 (1997-07-01), Mote, Jr.
patent: 5828824 (1998-10-01), Swoboda

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