Test system algorithmic program generators

Details Test system algorithmic program generators Test system algorithmic program generators

2006-11-28

2006-11-28

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07143326

ABSTRACT:
Testing an integrated circuit (IC) device, for example, an IC that includes an embedded memory, may involve specifying one or more test parameters including at least one of a pipeline depth data (e.g., latency delay information) and a data width data (e.g. corresponding to a data width of an embedded memory), generating a test sequence by associating test parameters with a test pattern, and applying the generated test sequence to the integrated circuit device. A test system for testing ICs having embedded memories may include multiple test patterns and multiple data structures, each data structure defining one or more test parameters including at least one of a pipeline depth and a data width, an algorithmic pattern generator, and software for controlling the algorithmic pattern generator to generate a test sequence by associating a specified data structure with a specified test pattern.

REFERENCES:
patent: 5491673 (1996-02-01), Okayasu
patent: 5535164 (1996-07-01), Adams et al.
patent: 5581177 (1996-12-01), Hussey et al.
patent: 5835969 (1998-11-01), Inagaki et al.
patent: 5883905 (1999-03-01), Eastburn
patent: 6237021 (2001-05-01), Drummond
patent: 6249889 (2001-06-01), Rajsuman et al.
patent: 6266750 (2001-07-01), DeMone et al.
patent: 6275057 (2001-08-01), Takizawa
patent: 2002/0166098 (2002-11-01), Chang et al.
patent: 199 48 388 (1998-10-01), None
patent: 19948388 (1998-10-01), None
patent: 0847060 (1998-06-01), None
patent: 0859367 (1998-08-01), None
patent: 11-038100 (1999-02-01), None
Iyengar et al. ‘Huffman encoding of test sets for sequential circuits,’ IEEE Transactions on Instrumentation and Measurement, Feb. 1998, pp. 21-25, vol. 47, Issue: 1.
PCT International Search Report, Apr. 9, 2003.
R. McConnell, U. Möller and D. Richter, “How We Test Siemens' Embedded DRAM Cores,” 1998, IEEE.
T. Falter and D. Richter, “Overview of Status and Challenges of System Testing on Chip with Embedded DRAMS,” 2000, Elsevier Science Ltd.
J. Dreibelbis, “Processor-Based Built-In Self-Test for Embedded DRAM,” 1998, IEEE.
S. Miyano, K. Sato and K. Numata, “Universal Test Interface for Embedded-DRAM Testing,” 1999, IEEE.

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