Test structures for stacking dies having through-silicon vias

Details Test structures for stacking dies having through-silicon vias Test structures for stacking dies having through-silicon vias

2007-03-19

2009-10-06

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257SE23011, C257S686000

Reexamination Certificate

active

07598523

ABSTRACT:
A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.

REFERENCES:
patent: 7439615 (2008-10-01), Ruckerbauer
patent: 2002/0036338 (2002-03-01), Matsuo et al.
patent: 2008/0073747 (2008-03-01), Chao et al.

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