Test structure used to measure metal bottom coverage in trenches

Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed

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438 18, G01R 3126, H01L 2166

Patent

active

061271934

ABSTRACT:
A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

REFERENCES:
patent: 5900645 (1999-05-01), Yamada
patent: 5963784 (1999-10-01), Bothra et al.
Article entitled, "Polycrystalline Thin Films--Structure, Texture, Properties and Applications III", Author: Besser et al., Mar. 1997, pp. 313-318.
Article entitled, "Advanced Metallization and Interconnect Systems for ULSI Applications in 1996", Author: Havemann et al., Oct. 1996, pp. 89-95.

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