Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-12-20
2005-12-20
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S224000, C438S227000
Reexamination Certificate
active
06977195
ABSTRACT:
For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.
REFERENCES:
patent: 5455450 (1995-10-01), Leduc
patent: 6803644 (2004-10-01), Minami et al.
Bush John J.
Dawson Robert
Qi Wen-Jie
Choi Monica H.
Dang Phuc T.
FASL LLC
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