Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2005-05-24
2005-05-24
Sarkar, Asok Kumar (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C324S071100, C438S014000, C438S018000
Reexamination Certificate
active
06897475
ABSTRACT:
This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. In other aspects, this disclosure provides a method of manufacturing a test structure within a semiconductor wafer, and a method of evaluating stress-induced voiding of metals within a semiconductor wafer.
REFERENCES:
patent: 6570181 (2003-05-01), Graas et al.
patent: 6747445 (2004-06-01), Fetterman et al.
patent: 20040026693 (2004-02-01), McLaughlin et al.
patent: 20040129938 (2004-07-01), Landers et al.
Sarkar Asok Kumar
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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