Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-07
2006-11-07
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
07132325
ABSTRACT:
A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.
REFERENCES:
patent: 5285101 (1994-02-01), Kikuchi
patent: 5311051 (1994-05-01), Tukizi
patent: 5362663 (1994-11-01), Bronner et al.
patent: 5418738 (1995-05-01), Abadeer et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5543348 (1996-08-01), Hammerl et al.
patent: 5561373 (1996-10-01), Itoh
patent: 5654895 (1997-08-01), Bach et al.
patent: 5666049 (1997-09-01), Yamada et al.
patent: 5798649 (1998-08-01), Smayling et al.
patent: 5831446 (1998-11-01), So et al.
patent: 5841182 (1998-11-01), Linn et al.
patent: 5846848 (1998-12-01), Chih-Sheng et al.
patent: 5867033 (1999-02-01), Sporck et al.
patent: 5872449 (1999-02-01), Gouravaram et al.
patent: 5898629 (1999-04-01), Beffa et al.
patent: 5903012 (1999-05-01), Boerstler
patent: 6114182 (2000-09-01), Tabara
patent: 6124143 (2000-09-01), Sugasawara
patent: 6441396 (2002-08-01), Adams et al.
patent: 6465370 (2002-10-01), Schrems et al.
patent: 6624031 (2003-09-01), Abadeer et al.
patent: 6770535 (2004-08-01), Yamada et al.
patent: 6770907 (2004-08-01), Abadeer et al.
patent: 6825078 (2004-11-01), Huang
patent: 6987043 (2006-01-01), Kujirai et al.
patent: 7030440 (2006-04-01), Huang
patent: 2002/0025622 (2002-02-01), Schrems et al.
patent: 2003/0207537 (2003-11-01), Abadeer et al.
patent: 2004/0067614 (2004-04-01), Hidaka et al.
Hirth et al., Theory of Dislocations, John Wiley & Sons Publishers, Second Edition.
P.G. Neudeck et al., Breakdown Degradation Associated With Elementary Screw Dislocations in 4H-SIC p+ n Junction Rectifiers, Solid State Electronics, vol. 42, No. 12, 1998, pp. 2157-2164.
Satoh et al., Degradation of Dieletric Breakdown Field of Thermal SiO2 Films Due to Structural Defects in Czochralski Silicon Substrates, J. Appl. Phys. 79 (10), May 15, 1996, pp. 7944-7957.
H. Miura et al., New Mechanical Reliability Issues for Deep Submicron Devices, IEEE Semiconductor Manufacturing Technology Workshop, (Cat. No. 98EX1330), 1998, pp. 140-147.
H. Miura et al., Mechanical Stress Simulation During Gate Formation of MOS Devices Considering Crystallization Induced Stress of Phosphorus Doped Silicon Thin Films, Journal of Microelectronics, (UK), vol. 26, No. 2-3, Mar. 1995, pp. 249-253.
H. Miura et al., Mechanical Stress Simulation for Highly Reliable Deep Submicron Devices, IEICE Trans. Electron. (Japan), Inst. Elextron. Inf. & Commun. Eng., vol. E82-C, No. 6, Jun. 1999, pp. 830-838.
S. Wang et al., MOS Transistor With High Leakage Failure Caused by LOCOS Dislocation, Semiconductor Manufacturing Technology Workshop, Taiwan Semicond. Manuf. Company, Hsinchu, Taiwan, Oct. 1996, pp. 22-23.
S. H. Voldman et al., TLM: A Trench Leakage Monitor for a Four Megabit SPT DRAM Technology, IBM, Burlington, Technical Report, TR 19.90539, Jul. 1990.
M. Noguchi et al., 0.29 μm2Trench Cell Technologies for 1 Gbit DRAMs With Open/Folded Bit-Lane Layout and Selective Growth Technique, 1995 Symposium on VLSI Technology Digest of Technical Papers.
P. Bakeman et al., A High Performance 16-Mbit DRAM Technology, 1990 Symposium on VLSI Technology Digest of Technical Papers.
T. Pompl et al., Investigation of Ultra-Thin Gate Oxide Reliability Behavior by Separate Characterization of Soft Breakdown and Hard Breakdown, Proceedings of the International Reliability Physics Symposium, San Jose CA, Apr. 10-13, 2000, pp. 40-47.
Abadeer Wagdi W.
Adler Eric
Brown Jeffrey S.
Gauthier Jr. Robert J.
McKenna Jonathan M.
Lebentritt Michael
Lestrange Michael
Stevenson Andre′
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