Test quality through resource reallocation

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Details

C703S015000, C716S030000, C716S030000

Reexamination Certificate

active

07133816

ABSTRACT:
A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.

REFERENCES:
patent: 5928334 (1999-07-01), Mandyam et al.
patent: 6006028 (1999-12-01), Aharon et al.
Chandra et al., AVPGEN-A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems, vol. 3, No. 2, Jun. 1995, pp. 188-200.
Jantsch et al., “Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases”, Design Automation of Embedded Systems, vol. 5, No. 1, Kluwer Academic Publisher, Feb. 2000, pp. 1-34.
Geist et al., A Methodology for the Verification of a System On A Chip, DAC 99, New Orleans, Louisiana, 1999 ACM 1-58113-109-7/99/06. pp. 1-6.
“Model-Based Test Generation for Processor Verification,” Y. Lichtenstein, Y. Malka, A. Aharon, Sixth Innovative Applications of Artificial Intelligence Conference, Aug. 1994, (12 pages).
“AVPGEN—A Test Generator for Architecture Verification,” A. Chandra, et al., IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, No. 2, Jun. 1995, pp. 188-200.
“MPTG: A Portable Test Generator for Cache-Coherent Multiprocessors”, International Conference on Computers and Communications, 0-7803-2492-Jul. 1995, IEEE, pp. 38-44.
“Short Vs. Long—Size Does Make a Difference,” A. Hartman, S. Ur, and A. Ziv, in IEEE International High Level Design Validation and Test Workshop (HLDVT), 1999 (6 pages).
“Test Program Generation for Functional Verification of PowerPC Processors in IBM,” A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek, in 32nd Design Automation Conference, 1995 (7 pages).
“A Methodology for the Verification of a ‘System On A Chip’,” D. Geist, G.Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, K. Holtz, A. Long, D. King, and S. Barret, in 36th Design Automation Conference 1999, New Orleans, Louisiana, (6 pages).

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