Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-03-22
2011-03-22
Beausoliel, Robert (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S737000, C703S013000, C703S014000, C703S023000, C703S028000, C716S103000, C716S106000, C716S112000
Reexamination Certificate
active
07913143
ABSTRACT:
A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.
REFERENCES:
patent: 6567946 (2003-05-01), Nozuyama
patent: 7065690 (2006-06-01), Yoshida et al.
patent: 7139956 (2006-11-01), Nozuyama
patent: 7162674 (2007-01-01), Nozuyama
patent: 7308660 (2007-12-01), Nozuyama
patent: 2004/0133833 (2004-07-01), Nozuyama
patent: 2004/0205681 (2004-10-01), Nozuyama
patent: 2005/0010839 (2005-01-01), Takeoka et al.
patent: 2005/0182587 (2005-08-01), Sato et al.
patent: 2006/0005094 (2006-01-01), Nozuyama
patent: 2007/0201618 (2007-08-01), Nozuyama
patent: 2007/0260408 (2007-11-01), Nozuyama
patent: 2008/0120585 (2008-05-01), Nozuyama et al.
patent: 2006-010351 (2006-01-01), None
T.W. Williams and N.C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Trans. Comp., vol. C-30, pp. 987-988, Dec. 1981.
Sato, et al, Feasibility Evaluation of the Statistical Delay Quality Model, vol. J89-D, No. 8, pp. 1717-1728, 2006.
Sato, et al, Invisible Delay Quality—SDQM Model Lights Up what Could Not Be Seen, International Test Conference, 0-7803-9039-3, IEEE, 2005.
Nozuyama, et al, A Method of Estimating and Enhancing Test Quality Using Layout Information, The Institute of Electronics, Technical Report of IEICE, CPM2002-152 ICD2002-197, 2003.
Sengupta, et al, Defect-Based Test: A Key Enabler for Successful Migration of Structural Test, Intel Technology Journal Q1 '99.
Beausoliel Robert
Kabushiki Kaisha Toshiba
Merant Guerrier
Turocy & Watson LLP
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