Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-06-24
2004-09-07
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S414000, C257S467000, C257S528000, C257S633000, C257S798000, C438S014000, C438S015000, C438S404000
Reexamination Certificate
active
06787803
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to the field of fabricating semiconductor devices, and more particularly to a test pattern for measurement of low-k dielectric cracking thresholds.
BACKGROUND
As integrated circuit device dimensions shrink, low-k dielectrics are commonly adopted as the inter-metal dielectrics to lower the RC delay so as to optimize their electrical performance. There is, however, a trade off. The gain achieved by decreasing the K-value of the dielectric is made at the expense of decreasing the mechanical properties of the low-k dielectrics. One common material property, namely, the cracking threshold, is a good index indicating the possibility and/or the limit of the low-k dielectric suffering fatal cracks during the silicon processing. Currently, the cracking threshold is measured on blanket wafers or through a random search for cracking sites among the existing patterns. There are no known dedicated patterns that provide systematic and practical measurement of the cracking threshold for low-k dielectric materials on the pattern wafers.
SUMMARY OF THE INVENTION
The present invention provides a systematic and practical structure and method to measure the cracking threshold of the low-k dielectrics in pattern wafers. As a result, the present invention provides prompt and easy low-k inter-metal dielectric (IMD) screening for nano-scale integrated circuit (IC) manufacturing using many newly invented materials. The present invention can be implemented on one or more layers of experimental wafers to develop design parameters for production wafers or on production wafers to monitor the production baseline processes.
More specifically, the present invention provides a test structure/substructure that is used as part of a test pattern for determining a cracking threshold for a dielectric material on a substrate. The test pattern includes two or more test structures disposed on the substrate. Each test structure/substructure includes two metal structures separated by the dielectric material having a width which is different for each test structure. The cracking threshold will be approximately equal to the largest width of dielectric material that is cracked after processing.
The present invention also provides a method for determining a cracking threshold for a dielectric material. Two or more test structures are formed on the substrate. Each test structure includes two metal structures separated by the dielectric material having a width which is different for each test structure. A determination of whether the dielectric material between the two metal structures for each test structure has cracked during processing is then made. The cracking threshold is approximately equal to the largest width of dielectric material that is cracked. The cracking threshold can be measured by electrically probing the two metal structures in each test structure to measure a leakage current across the with of the dielectric material for each test structure. The cracking threshold can also be measured by optically inspecting the width of the dielectric material for each test structure.
REFERENCES:
patent: 5637186 (1997-06-01), Liu et al.
patent: 5981302 (1999-11-01), Alswede et al.
patent: 6028324 (2000-02-01), Su et al.
patent: 6329671 (2001-12-01), Tamaki et al.
patent: 6472236 (2002-10-01), Wang et al.
patent: 6605868 (2003-08-01), Ishiwata et al.
patent: 6613592 (2003-09-01), Chen et al.
patent: 6680484 (2004-01-01), Young
patent: 2002/0004288 (2002-01-01), Nishiyama
patent: 2002/0167071 (2002-11-01), Wang
patent: 2004/0048402 (2004-03-01), Ishii
patent: 522539 (2003-03-01), None
Huang Tai-Chun
Yao Chih-Hsiang
Everhart Caridad
Rocchegiani Renzo
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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