Test patterns and methods of controlling CMP process using...

Details Test patterns and methods of controlling CMP process using... Test patterns and methods of controlling CMP process using...

2005-04-05

2005-04-05

Kang, Donghee (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S620000, C257S797000, C438S011000, C438S014000, C438S015000, C438S018000

Reexamination Certificate

active

06875997

ABSTRACT:
A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

REFERENCES:
patent: 20020036356 (2002-03-01), Teshima et al.
patent: 20000045929 (2000-07-01), None
patent: 20000046956 (2000-07-01), None
English Abstract (2000-0046956).
English Abstract (2000-0045929).

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