Test pattern generating method and apparatus and storing...

Details Test pattern generating method and apparatus and storing... Test pattern generating method and apparatus and storing...

2004-10-18

2008-10-14

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07437646

ABSTRACT:
The present invention is a test pattern generating method. And the test pattern generating method provides a counting step for counting the number of faults becoming undetectable respectively, at each of states 0 and 1 that are able to be given to each of input pins of EOR gates when each of the EOR gates becomes a D frontier (different frontier) or a J frontier (justify frontier), a selecting step for selecting a state in which the number of faults becoming undetectable is smaller in the 0 and 1 states as an allocating state to the input pin, based on a counted result at the counting step, and step for generating the test pattern based on a selected state at the selecting step. With this, dynamic compaction can be effectively executed by restraining the increase of the number of test patterns.

REFERENCES:
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patent: 5390193 (1995-02-01), Millman et al.
patent: 5410552 (1995-04-01), Hosokawa
patent: 5958077 (1999-09-01), Banerjee et al.
patent: 6425104 (2002-07-01), Toumiya
patent: 6618117 (2003-09-01), Silverbrook
patent: 6658635 (2003-12-01), Tanimoto
patent: 7296249 (2007-11-01), Rinderknecht et al.
patent: 11052030 (1999-02-01), None

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