Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-29
2008-07-29
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
11158261
ABSTRACT:
A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
REFERENCES:
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5485471 (1996-01-01), Bershteyn
patent: 6567946 (2003-05-01), Nozuyama
patent: 6766473 (2004-07-01), Nozuyama
patent: 7065690 (2006-06-01), Yoshida et al.
patent: 11-025147 (1999-01-01), None
patent: 11-052030 (1999-02-01), None
patent: 2001-127163 (2001-05-01), None
patent: 2003-107138 (2003-04-01), None
U.S. Appl. No. 10/758,446, filed Jan. 2004, Nozuyama.
U.S. Appl. No. 10/678,975, filed Oct. 2003, Nozuyama.
Nozuyama, et al., “A Method for Estimating and Enhancing Test Quality Using Layout Information,” Technical Report of IEICE (Japan), vol. CPM2002-152, pp. 1-6, (2003).
Sengupta, et al., “Defect-Based Test: A Key Enabler For Successful Migration to Structural Test,” Intel Technology Journal, pp. 1-14, (1999).
Stroud, et al., “Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development,” Proc. IEEE International Test Conference, pp. 760-769, (2000).
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Kerveros James C
LandOfFree
Test pattern generating apparatus, method for automatically... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test pattern generating apparatus, method for automatically..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generating apparatus, method for automatically... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3912818