Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-05-05
2000-07-11
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060888245
ABSTRACT:
A test pattern generating apparatus generates a test pattern for evaluating whether or not source data and a bit synchronous clock signal SCK are transmitted normally through a bus connecting a plurality of terminal units for transmitting and receiving source data. A test pattern generating circuit 33 generates predetermined test pattern data which are predetermined as the test pattern, based on the bit synchronous clock signal and a frame synchronous clock signal LRCK and outputs the test pattern data, bit synchronous clock signal and frame synchronous clock signal to the bus.
REFERENCES:
patent: 4247941 (1981-01-01), Raymond
patent: 5383195 (1995-01-01), Spence et al.
patent: 5909448 (1999-06-01), Takahashi
Ito Narihisa
Nakatsugawa Yoshinori
Tatara Hirokazu
Nguyen Hoa T.
Yazaki -Corporation
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