Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-02-02
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06651205
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a test pattern converter and conversion method thereof for converting the format of test patterns used to test semiconductor devices such as LSIs, and more particularly, to a test pattern converter and conversion method thereof for converting cycle-based test patterns into event-based test patterns with use of a tester simulator.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as LSIs, a semiconductor test system provides input test signals to a semiconductor device under test. The output signal from the semiconductor device under test resulting from the input test signal is sampled at timings of strobes, and compared with predetermined expected values to check if the two signals match with one another, thereby determining whether the semiconductor device under test functions correctly. Generally, the input test signal and strobe are collectively called a “test pattern”.
Many different test patterns are produced depending on particular test types or test purposes for semiconductor devices to be tested, and are stored in a storage medium such as a hard disc as test pattern files. Prior to beginning a test for semiconductor devices, the applicable test patterns are installed in the semiconductor test system, where the test patterns are generated upon starting the test operation and the test patterns are applied to the semiconductor device under test.
The majority of the existing semiconductor test systems today are structured to generate test patterns using test pattern data described in a cycle format (hereafter “cycle-based test system”). The cycle format is a method of formulating pattern data in which the test patterns such as input test signals to be generated by the semiconductor test system are divided into each predetermined time (test cycle), and defining the kinds of waveforms, logic, and timings with respect to those test cycles. The details of the cycle format will be explained later.
Recently, an event-based semiconductor test system (hereafter “event-based test system”) structured by an architecture different from the cycle-based test system has been proposed. The event-based test system generates test patterns by using the test pattern data described in an event format. The event format expresses the test pattern waveforms to be generated by the semiconductor test system by each and every change point (i.e., rising edges, falling edges) of the waveforms and its timing data. Therefore, processes such as dividing the test patterns at every test cycle are not involved in this format. The details of the event format will be explained later.
In the case of using the cycle format, test program descriptions become complicated and the execution of the test program will require a complicated test system operation, although the amount of data in the test program becomes small. On the contrary, in the case of using the event format, the test program description and its execution are more simplified, and the flexibility of the test system becomes greater. However, the amount of data in the event-based test patterns can increase, therefore requiring a larger memory capacity in the test system which increases the test system cost. In recent years, however, memory capacity per unit price has been dramatically increasing, thus, the cost increase of memories is no longer thought to be a major problem.
FIG. 1
is a block diagram showing an example of a basic structure of the cycle-based test system. In this diagram, a tester processor
11
is an exclusive processor installed in the test system, and controls the operation of the test system through a tester bus. Based on pattern data from the tester processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. Based on the waveform data from the pattern generator
12
and the timing data from the timing generator
13
, the wave formatter
14
formats the test patterns. The test patterns produced by the wave formatter
14
are then supplied to a device under test (DUT)
19
through a driver
15
provided in a pin electronics circuit
20
.
DUT
19
responds to the test patterns and generates output signals. The output signals are transmitted to an analog comparator
16
in the pin electronics circuit
20
. At timings of the strobes, the analog comparator
16
converts the output signals from DUT
19
into logic signals with respect to predetermined threshold levels, and sends the result to a logic comparator
17
. In the logic comparator
17
, the logic data from DUT
19
and expected logic data formed by the pattern generator
12
are compared with each other. The results of comparison are stored in a failure memory
18
in the addresses corresponding to the addresses of a memory which stores the test patterns or to the addresses of DUT
19
.
FIG. 2
is a block diagram showing an example of a basic structure of the event-based test system. The event-based test system in this example is comprised of a host computer
42
, a bus interface
43
, an internal bus
45
, an address control logic
48
, a failure memory
47
, an event memory configured by an event count memory
50
and an event vernier memory
51
, an event summing and scaling logic
52
, an event generator
24
, and a pin electronics circuit
26
. A device under test (DUT)
28
is connected to the pin electronics circuit
26
.
As an example, the host computer
42
is a work station with a UNIX operating system. The host computer
42
functions as a user interface for the user to instruct the start and stop of the test, to load test programs and other test conditions, or to conduct the test result analysis at the host computer. The host computer
42
interfaces with the hardware test system through the system bus
44
and the bus interface
43
.
The internal bus
45
is a bus within the hardware test system. As an example, the address control logic
48
is a tester processor exclusive to the hardware test system, and therefore the user cannot have access to it. Based on the test programs and test conditions from the host computer
42
, the address control logic
48
supplies the instructions to other functional blocks within the test system. The failure memory
47
stores the test result such as failure information concerning the DUT
28
in the addresses defined by the address control logic
48
. The information stored in the failure memory
47
is used in a failure analysis stage of the device under test.
The address control logic
48
provides the address data to the failure memory
47
and the event memory comprised of the event count memory
50
and the event vernier memory
51
. The event memory stores the event timing data which expresses the timing of each event (i.e., change point of 1 to 0 or 0 to 1). For example, the timing data for each event is divided into integral data representing an integer multiple of a reference clock period and fractional data representing a fraction of the reference clock period. For example, the integral data is stored in the event count memory
50
and the fractional data is stored in the event vernier memory
51
.
The event summing and scaling logic
52
accumulates the event timing data and modifies a multiplication ratio of the timing data, and expresses the timing of each event as a total timing (delay time) from a predetermined reference time. Based on the total timing data, the event generator
24
generates a test pattern (drive event), and provides the test pattern to DUT
28
through the pin electronics circuit
26
. By comparing the response output signals of DUT
28
with the expected pattern (sampling event), the test system determines pass/fail regarding a particular pin of DUT
28
.
As explained above, in the event-based test system, the data configuration in a test program used therein is simple, and therefore, allows the test program to be easily created as well as enables the test system to configure in such a way that each test pin in the test system functions independ
Abraham Esaw
Advantest Corp.
De'cady Albert
Muramatsu & Associates
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