Test pattern compression with pattern-independent...

Details Test pattern compression with pattern-independent... Test pattern compression with pattern-independent...

2007-11-27

2007-11-27

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000

Reexamination Certificate

active

11095222

ABSTRACT:
The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.

REFERENCES:
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6041429 (2000-03-01), Koenemann
patent: 6272653 (2001-08-01), Amstutz
patent: 6684358 (2004-01-01), Rajski et al.
patent: 6950974 (2005-09-01), Wohl et al.
patent: 7093175 (2006-08-01), Rajski et al.
patent: 481097 (1992-04-01), None
Hellebrand, S. et al., “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Transactions on Computers, vol. 44, No. 2, Feb. 1995, pp. 223-233.
Decompression of test data using variable-length seed LFSRs Zacharia, N.; Rajski, J.; Tyszer, J.;□□VLSI Test Symposium, 1995. Proceedings., 13th IEEE Apr. 30-May 3, 1995 pp. 426-433.

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