Test pattern compression for an integrated circuit test...

Details Test pattern compression for an integrated circuit test... Test pattern compression for an integrated circuit test...

2006-09-19

2006-09-19

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07111209

ABSTRACT:
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

REFERENCES:
patent: 3614400 (1971-10-01), Farnett
patent: 3700869 (1972-10-01), Low et al.
patent: 4503537 (1985-03-01), McAnney
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4536881 (1985-08-01), Kasuya
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4754215 (1988-06-01), Kawai
patent: 4785410 (1988-11-01), Hamatsu et al.
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 4860236 (1989-08-01), McLeod et al.
patent: 4959832 (1990-09-01), Bardell, Jr.
patent: 4974184 (1990-11-01), Avra
patent: 5090035 (1992-02-01), Murase
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5167034 (1992-11-01), MacLean, Jr. et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5258986 (1993-11-01), Zerbe
patent: 5268949 (1993-12-01), Watanabe et al.
patent: 5301199 (1994-04-01), Ikenaga et al.
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5349587 (1994-09-01), Nadeau-Dotsie et al.
patent: 5369648 (1994-11-01), Nelson
patent: 5394405 (1995-02-01), Savir
patent: 5412665 (1995-05-01), Gruodis et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5416783 (1995-05-01), Broseghini et al.
patent: 5446683 (1995-08-01), Mullen et al.
patent: 5450414 (1995-09-01), Lin
patent: 5524114 (1996-06-01), Peng
patent: 5574733 (1996-11-01), Kim
patent: 5586125 (1996-12-01), Warner
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5612963 (1997-03-01), Koenemann et al.
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5631913 (1997-05-01), Maeda
patent: 5680543 (1997-10-01), Bhawmik
patent: 5694402 (1997-12-01), Butler et al.
patent: 5701308 (1997-12-01), Attaway et al.
patent: 5717702 (1998-02-01), Stokes et al.
patent: 5719913 (1998-02-01), Maeno
patent: 5748497 (1998-05-01), Scott et al.
patent: 5790562 (1998-08-01), Murray et al.
patent: 5790626 (1998-08-01), Johnson et al.
patent: 5812561 (1998-09-01), Giles et al.
patent: 5831992 (1998-11-01), Wu
patent: 5867507 (1999-02-01), Beebe et al.
patent: 5870476 (1999-02-01), Fischer
patent: 5872793 (1999-02-01), Attaway et al.
patent: 5883906 (1999-03-01), Turnquist et al.
patent: 5899961 (1999-05-01), Sundermann
patent: 5905986 (1999-05-01), Rohrbaugh et al.
patent: 5938784 (1999-08-01), Kim
patent: 5974179 (1999-10-01), Caklovic
patent: 5974433 (1999-10-01), Currie
patent: 5983380 (1999-11-01), Motika et al.
patent: 5991898 (1999-11-01), Rajski et al.
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6006349 (1999-12-01), Fujisaki
patent: 6014763 (2000-01-01), Dhong et al.
patent: 6026508 (2000-02-01), Craft
patent: 6041429 (2000-03-01), Koenemann
patent: 6055658 (2000-04-01), Jaber et al.
patent: 6061818 (2000-05-01), Touba et al.
patent: 6072823 (2000-06-01), Takakusaki
patent: 6122761 (2000-09-01), Park
patent: 6141669 (2000-10-01), Carleton
patent: 6158032 (2000-12-01), Currier et al.
patent: 6178532 (2001-01-01), Pierce et al.
patent: 6199182 (2001-03-01), Whetsel
patent: 6240432 (2001-05-01), Chuang et al.
patent: 6256759 (2001-07-01), Bhawmik et al.
patent: 6286119 (2001-09-01), Wu et al.
patent: 6300885 (2001-10-01), Davenport et al.
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6330681 (2001-12-01), Cote et al.
patent: 6353842 (2002-03-01), Rajski et al.
patent: 6385750 (2002-05-01), Kapur et al.
patent: 6539409 (2003-03-01), Rajski et al.
patent: 6543020 (2003-04-01), Rajski et al.
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6684358 (2004-01-01), Rajski et al.
patent: 6708192 (2004-03-01), Rajski et al.
patent: 6829740 (2004-12-01), Rajski et al.
patent: 2002/0112199 (2002-08-01), Whetsel
patent: 2002/0124217 (2002-09-01), Hiraide et al.
patent: 0372226 (1990-06-01), None
patent: 0438322 (1991-07-01), None
patent: 0481097 (1992-04-01), None
patent: 0887930 (1998-12-01), None
patent: 01-239486 (1989-09-01), None
patent: 03-002579 (1991-01-01), None
patent: 4-236378 (1992-08-01), None
patent: 05-215816 (1993-08-01), None
patent: 9-130378 (1997-05-01), None
patent: 11-030646 (1999-02-01), None
patent: 11-153655 (1999-09-01), None
patent: WO 01/38889 (2001-05-01), None
patent: WO 01/39254 (2001-05-01), None
Langdon, Jr., “An Introduction to Arithmetic Coding,”IBM J. Res. Develop.,vol. 28, No. 2, pp. 135-149 (Mar. 1984).
P.H. Bardell, “Design Considerations for Parallel Pseudorandom Pattern Generators”, Journal of Electronic Testing: Theory and Applications, 1,73-87 (1990).
I. Hamzaoglu, J. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL., 1999 IEEE, pp. 260-267.
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, “Built-in Test for Circuits With Scan Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers”,IEEE Trans. On Computers,vol. C-44, pp. 223-233, Feb., 1995.
S. Hellebrand, B. Reeb, S. Tarnick, H-J Wunderlich, “Pattern Generation for a Deterministic BIST Scheme”, pp. 88-94, 1995 IEEE.
B. Koenemann c/o IBM Corp. , B56/901, “LFSR-Coded Test Patterns for Scan Designs”,Proceedings of European Test Conference,pp. 237-242, 1991.
J. Rajski,J. Tyszer, N. Zacharia, “Decompression of Test Data Using Variable-Length Seed LFSRs”, Microelectronics and Computer Systems Laboratory, McGill University, Montreal, Canada, 1995 IEEE, pp. 426-433.
J. Rajski, J. Tyszer, N. Zacharia, “Test Data Decompression for MultipLe Scan Designs with Boundary Scan,” IEEE Transactions on Computers, vol. 47, No. 11, Nov. 1998, pp. 1188-1200.
J. Rajski and J. Tyszer, “Design of Phase Shifters for BIST Applications”,Proc. VLSI Test Symposium,pp. 218-224, 1998, IEEE.
J. Rajski, N. Tamarapalli, J. Tyszer, “Automated Synthesis of Large Phase Shifters for Built-In Self-Test,” International Test Conference, Paper 41.1, pp. 1047-1056, IEEE 1998, paper 61.1.
Venkataraman, Rajski, Hellebrand, and Tarnick, “An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers”, pp. 572-577, 1993 IEEE.
P.H. Bardell, W.H. McAnney, J. Savir, Built in test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
W-B, Jone and S.R. Das, “Space compression method for built-in self testing of VLSI circuits,”Int. Journal of Computer Aided VLSI Design,vol. 3, pp. 309-322, 1991.
H.J. Wunderlich, “On computing optimized input probabilities for random tests,” Proc. DAC pp. 392-398, 1987, paper 24.2.
N.R. Saxena and J.P. Robinson, “Accumulator compression testing,”IEEE Trans. Comput.,vol. C-35, No. 4, pp. 317-321, 1986.
J.P. Hayes, “Check sum test methods,”Proc. FTCS,pp. 114-120, 1976.
J. Savir, “Syndrome-testable design of combinational circuits,”IEEE Trans. Comput.vol. C-29, No. 6, pp. 442-451, 1980.
Y.K. Li and J.P. Robinson, “Space compression methods with output data modification,”IEEE Trans. CAD if Integrated Circuits and Systems,vol. CAD-6, No. 2, pp. 290-294, 1987.
J.E. Smith, “Measures of the effectiveness of fault signature analysis,”IEEE Trans. Comput.,vol. C-29, No. 6, pp. 510-514, Jun., 1980.
K

Affiliated with

Also associated with

Rating

Test pattern compression for an integrated circuit test... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test pattern compression for an integrated circuit test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern compression for an integrated circuit test... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3546555