Test parallelism increase by tester controllable switching...

Details Test parallelism increase by tester controllable switching... Test parallelism increase by tester controllable switching...

2008-04-22

2008-04-22

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C324S754090, C714S718000

Reexamination Certificate

active

07362632

ABSTRACT:
Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

REFERENCES:
patent: 6449740 (2002-09-01), Yoshie
patent: 6711042 (2004-03-01), Ishikawa
patent: 7106081 (2006-09-01), Mayder et al.

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