Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-14
2009-10-27
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S720000, C714S728000, C714S729000, C714S738000, C714S739000
Reexamination Certificate
active
07610527
ABSTRACT:
Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.
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Naruse et al., On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding, 2003, IEEE, pp. 1060-1068.
Zacharia et al., Decompression of Test Data Using Variable-Length Seed LFSRs, 1995, IEEE, pp. 426-433.
Wang et al., X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors, Jul. 2008, IEEE, vol. 57, No. 7, pp. 978-989.
Balakrishnan Kedarnath J
Chakradhar Srimat T
Wang Seongmoon
Kolodka Joseph J.
NEC Laboratories America, Inc.
Tabone, Jr. John J
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