Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-19
2001-04-03
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06212115
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to test systems, and in particular, to test systems for Static Random Access Memory (SRAM) that enable testing at the chip level for specific failure modes.
BACKGROUND INFORMATION
Memory arrays implemented in integrated circuits are characterized by a matrix of storage cells that are bussed together to make a memory chip. Each memory cell is coupled with select transistors to bussed lines that connect all the cells together to form the memory array. When a word line (row select) is activated, all the memory cells in a row have their outputs coupled to a bit line (column select) or lines with select transistors. The stored data in a memory cell alters the pre-charged voltage on a bit line when the particular cell is accessed or “read”. The bit line is coupled to a sense amplifier which conditions and then couples the read data external to the memory array.
In the fabrication of SRAM chips, variations in the manufacturing process may be responsible for different failure conditions. A high yield manufacturing facility requires tight control of the process parameters in the manufacturing steps used to make the SRAM chips. An SRAM typically has two bit lines (a normal and a complement) in each column that are used to coupled to the SRAM storage cells. These bit lines use the same type of metallic interconnection layer. When a fault occurs within an SRAM, it is important to know the failure mechanism. A fault may have several causes and it is important that the correct process involved in the failure be identified. When the correct process is identified, proper controls may be put in place to minimize quality problems.
One of the techniques used to determine the root cause of failures within an SRAM array is to mount the chip on a special substrate and polish thin layers of the chip away using destructive grinding. This process exposes the internal chip structure so it may be observed under a microscope. Understanding before hand what type of SRAM chip failure one is looking for may aid in how the above destructive process is carried out.
The storage cell of an SRAM is typically made up of a circuit employing two cross-coupled inverters as shown in FIG.
1
B. The cross-coupled inverters
106
and
108
make up the SRAM storage cell
107
in the exemplary SRAM storage circuit
112
When SRAM storage cell
107
is read, the read out voltage level coupled to bit line BIT
103
should always be the complement of the voltage level on bit line XBIT
104
. An inverter, like
106
or
108
, may be constructed using an exemplary circuit connection of transistors
101
and
102
of inverter
100
in FIG.
1
A. Bit lines (e.g., BIT
103
and XBIT
104
) extend through an entire array and are used to read out information in each SRAM storage cell (e.g., SRAM storage cell
107
) which may be coupled to the bit lines. When the exemplary word line WL
111
is selected, transistors
105
and
109
are turned on and the voltage states of the cross-coupled inverters
106
and
108
are coupled onto BIT
103
and XBIT
104
.
Referring to
FIG. 1B
, one can observe that a variety of faults may cause the read out of data from a particular storage cell to fail. For example, the cross-coupled inverters
106
and
108
may be faulty or transistor
105
or
109
may fail. Likewise various interconnections to transistors
105
and
109
, inverters
106
and
108
, BIT
103
and XBIT
104
may also fail.
Knowing that the SRAM storage circuit
112
failed because of interconnect contact failure would be valuable because it would point to particular process steps that may be at fault. A method for determining that an SRAM had contact failures would improve the failure analysis of SRAMS.
SUMMARY OF THE INVENTION
Two test probes are applied to the bit lines of an SRAM storage cell. The first test probe applies a voltage to one of the two bit lines in an SRAM storage circuit while the word line of the SRAM storage circuit is selected. The applied first test probe voltage forces the other complement bit line (the one under test) to a logic zero or logic one by forcing the input to the cross-coupled inverter whose output is coupled to the bit line under test. A conduction path should exist between the bit line under test and a word line select transistor and a transistor in a cross-coupled inverter. A variable voltage is applied to the bit line under test and a resulting current is measured for each applied voltage level. By comparing test results to a voltage versus current curve of a “good” SRAM storage circuit, information about the contacts and other aspects of the SRAM storage circuit may be deduced. Analysis of the applied voltage and the resulting currents for the bit line connections to the SRAM storage circuit gives an insight into various types of possible failures or circuit degradations.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5845059 (1998-12-01), McClijre
patent: 6002623 (1999-12-01), Stave et al.
Advanced Micro Devices , Inc.
Dinh Son T.
Winstead Sechrest & Minick P.C.
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