Test key for monitoring gate conductor to deep trench...

Details Test key for monitoring gate conductor to deep trench... Test key for monitoring gate conductor to deep trench...

2007-03-13

2007-03-13

Parker, Kenneth (Department: 2815)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S018000, C257S048000, C257S905000, C257S908000, C257SE23179

Reexamination Certificate

active

10904652

ABSTRACT:
A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern surrounded by second assistant bit line contact patterns is disposed on the left side of a second deep trench capacitor. The test key has a mirror symmetric line. The first assistant bit line contact patterns and second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A signal-in bit line is connected to the first bit line contact and a signal-out bit line is connected to the second bit line contact. The rest rows of the bit lines are dummy bit lines and floating.

REFERENCES:
patent: 6617180 (2003-09-01), Wang
patent: 6801462 (2004-10-01), Chang et al.
patent: 2005/0040398 (2005-02-01), Kowalski et al.

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