Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2003-06-23
2004-11-30
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000
Reexamination Certificate
active
06825053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test key and particularly to a test key and method for validating the position of a word line structure overlaying the deep trench capacitor in a DRAM.
2. Description of the Prior Art
The essential charge storage devices in a DRAM (Dynamic Random Access Memory) are frequently implemented by trench capacitors. The trench capacitor is formed in the substrate and has a capacitance proportional to the depth of the trench. That is to say, by increasing the depth of the trench, which results in a larger surface area of the “plates”, the trench capacitor provides a higher capacitance.
FIG. 1
is a diagram showing the layout of a conventional DRAM. A trench capacitor
10
is disposed beneath the passing word line. A transistor
14
is coupled to a node
16
of the trench capacitor
10
through a diffusion region
18
. A diffusion region
20
is coupled to a plug
22
. The plug
22
is coupled to a bit line (not shown). Thus, data is read from or written into the trench capacitor
10
through the node
16
by operation of the transistor
14
. The transistor
14
is controlled by voltages on the word line
12
. When a high voltage level is on the word line
12
, a conductive channel is formed below the word line
12
so that a current flows from or to the node
16
through the diffusion regions
18
and
20
, whereby the data is read from or written into the capacitor
10
.
FIG. 2
shows a cross section along the line AA in FIG.
1
. An STI (Shallow Trench Isolation)
28
is formed in the substrate and trench capacitor to define an active area and isolate the trench capacitor
10
from the word line
12
formed later. After formation of the word line
12
, the diffusion regions
18
and
20
, used as a source and drain, on two sides of the word line
12
are formed by ion implantation with masking of the word line
12
and STI
28
. Thus, the position of the word line
12
overlaying the trench capacitor
10
has great impact on the profiles of the source and drain. For the DRAM having trench capacitors used as storage devices, an improper overlay of the word line and capacitor results in current leakage between adjacent memory cells or even defective cells. Validating the position of the word line is an essential step for DRAM manufacturing.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a test key and method for validating the position of a word line structure overlaying the deep trench capacitor in a DRAM.
The present invention provides a test key for validating the position of a word line overlaying a trench capacitor, which is deposited in a scribe line region of a wafer, the test key comprises a trench capacitor deposited in the scribe line region and has a buried plate, a rectangular word line deposited in the scribe line region and covers a portion of the trench capacitor, a first and second passing word line deposited above the trench capacitor, a first and second doping region respectively deposited between the rectangular word line and the first passing word line, and the rectangular word line and the second passing word line, a first plug coupled to the first doping region, a second plug coupled to the second doping region, and a third plug coupled to the buried plate.
The present invention further provides a method for validating the position of a word line overlaying a trench capacitor, comprising the steps of providing a wafer having at least one scribe line region and a memory cell region, forming a test key in the scribe line region and a plurality of memory cells in the memory cell region, wherein the test key comprises a trench capacitor deposited in the scribe line region and has a buried plate, a rectangular word line deposited in the scribe line region and covers a portion of the trench capacitor, a first and second passing word line deposited above the trench capacitor, a first and second doping region respectively deposited between the rectangular word line and the first passing word line, and the rectangular word line and the second passing word line, a first plug coupled to the first doping region, a second plug coupled to the second doping region, and a third plug coupled to the buried plate, measuring a first current between the first and third plug resulting from applying a predetermined voltage difference between the first and third plug, applying a predetermined voltage level on the rectangular word line and floating the second plug, and a second current between the second and third plug resulting from applying the predetermined voltage difference between the second and third plug, applying the predetermined voltage level on the rectangular word line and floating the first plug, and validating the position of the rectangular word line by the measured first and second currents.
REFERENCES:
patent: 5914512 (1999-06-01), Huang
patent: 6310361 (2001-10-01), Lichter
patent: 6339228 (2002-01-01), Iyer et al.
Huang Chien-Chang
Jiang Bo Ching
Ting Yu-Wei
Wu Tie Jiang
Nanya Technology Corporation
Quintero Law Office
Vu Hung
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