Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-02
2007-10-02
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010, C324S1540PB
Reexamination Certificate
active
10207196
ABSTRACT:
A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.
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Britt Cynthia
Broadcom Corporation
Sterne Kessler Goldstein & Fox P.L.L.C.
Tabone, Jr. John J.
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