Test generation methods for reducing power dissipation and...

Details Test generation methods for reducing power dissipation and... Test generation methods for reducing power dissipation and...

2011-01-04

2011-01-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000

Reexamination Certificate

active

07865792

ABSTRACT:
Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.

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