Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-06-06
2006-06-06
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000
Reexamination Certificate
active
07058864
ABSTRACT:
Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code that, when compiled into machine test code, interfaces with the test engine. The machine test code is executed with the processor to test the memory cache to detect one or more faulty memory blocks in the memory cache. If any of the faulty memory blocks are detected, the test engine is instructed, through the machine test code, to set one or more bits in registers to functionally replace the faulty memory blocks with redundant blocks of the memory cache.
REFERENCES:
patent: 6351789 (2002-02-01), Green
patent: 6426904 (2002-07-01), Barth et al.
patent: 6519725 (2003-02-01), Huisman et al.
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6892328 (2005-05-01), Klein et al.
patent: 6928638 (2005-08-01), Parvathala et al.
Gratias Raymond Paul
McHardy William Bryson
Miller Kevin
Nugent Brian
Hewlett Packard Company
Hewlett--Packard Development Company, L.P.
Ton David
LandOfFree
Test for processor memory cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test for processor memory cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test for processor memory cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3644421