Test data compression method for system-on-chip using...

Details Test data compression method for system-on-chip using... Test data compression method for system-on-chip using...

2007-08-15

2010-06-01

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S715000, C714S741000, C714S025000, C714S724000, C714S738000, C714S739000, C714S733000, C714S030000, C714S726000, C714S727000, C709S220000, C709S200000, C716S030000, C716S030000, C716S030000, C703S023000, C324S601000

Reexamination Certificate

active

07730373

ABSTRACT:
A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

REFERENCES:
patent: 7159161 (2007-01-01), Lee et al.
patent: 7225376 (2007-05-01), Appinger et al.
patent: 7555688 (2009-06-01), Alvamani et al.
patent: 2006/0236176 (2006-10-01), Alyamani et al.
patent: 2007/0260952 (2007-11-01), Devanathan et al.
patent: 2007/0300110 (2007-12-01), Rajski et al.
Volkerink et al, “Efficient seed utilization for reseeding based compression,” in Proc. VTS 2003, pp. 232-237.

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