Test converage of embedded memories on semiconductor substrates

Details Test converage of embedded memories on semiconductor substrates Test converage of embedded memories on semiconductor substrates

1997-02-04

1998-07-21

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

371 212, G11C 2900

Patent

active

057843236

ABSTRACT:
The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.

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