4. Static information storage and retrieval
  5. Associative memories
  6. Ferroelectric cell

Garrett Stephen Koch

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Enhanced built-in self-test circuit and method

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Patent

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Memory array built-in self-test circuit having a programmable pa

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Memory array built-in self-test circuit having a programmable pa

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Patent

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Method and apparatus for real time two dimensional redundancy al

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Method and apparatus for real time two dimensional redundancy al

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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