Test circuit for testing a circuit

Details Test circuit for testing a circuit Test circuit for testing a circuit

2002-05-02

2003-09-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189070

Reexamination Certificate

active

06618305

ABSTRACT:

This application claims the benefit of German application number 101 21 309.3, filed May 2, 2001, currently pending, the disclosure of which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
The invention relates to a test circuit for testing a circuit to be tested, in particular a test circuit for testing a synchronous memory operating at a high frequency.
BACKGROUND OF THE INVENTION
FIG. 1
a
shows a test arrangement according to the prior art. A circuit to be tested (DUT: Device Under Test) is tested in respect of its functionality by an external test unit. The circuit to be tested is, for example, a synchronous memory module containing a multiplicity of memory cells. The external test unit applies control signals for testing the synchronous memory module via a control bus and addresses the memory cells to be tested within the memory module via the address bus. A test data generator contained in the external test unit generates test data patterns which, in a writing operating mode, are applied via a data bus to the circuit to be tested and are written to the addressed memory cells. Afterward, in a reading operating mode, the data are read out again from the addressed memory cells and transmitted back to the external test unit via the data bus. The test unit compares the read-out test data internally with reference test data and identifies defective memory cells on the basis of discrepancies between the reference test data and the read-out data.
In order to increase the maximum possible data transmission rate in the case of point-to-point data connections, the signal lines of the data bus, which comprises d data signal lines, for example, are designed as differential signal lines. In this case, for each data signal, in parallel the corresponding inverted data signal is passed via a dedicated signal line.
FIG. 1
b
shows an example of a data line pair of the data bus between the circuit to be tested DUT and the external test unit. The data line pair of the differential data bus has a first data signal line for the transmission of a data signal sig and a second data signal line for the transmission of a data signal {overscore (sig)} inverted with respect thereto. The two illustrated data signal lines of the data line pair between the circuit to be tested DUT and the test unit have a length L.
The differential signal transmission makes it possible for the input and output stages of the circuit to be tested DUT and of the test unit to be constructed simply in terms of line technology, at the same time the input and output stages and also the transmission link being insensitive to jitter of the signal edges and drifts of the DC voltage levels.
The relatively long data signal lines between the test unit and the circuit to be tested DUT give rise to signal propagation time delays of the data signals and to signal propagation time differences between the transmitted data signal and the transmitted inverted data signal with respect thereto. The propagation time differences are a consequence of different line lengths of the two data lines of a data line pair, different parasitic capacitances or inductances and different manufacturing tolerances. Since, in the case of the test arrangement illustrated in
FIG. 1
b,
signal propagation time differences between the data signal and the data signal transmitted in inverted form with respect thereto cannot be calibrated out, these signal propagation time differences lead to losses in the temporal accuracy of the entire test arrangement and thus to yield losses during testing. The additional inaccuracy effected by the signal propagation time differences is in excess of 50 pico seconds in many cases. When testing high-frequency memory modules which operate with clock frequencies of a few hundred megahertz, such signal propagation time delays cause test errors.
Therefore, the test arrangement illustrated in
FIG. 2
was proposed. In order to compensate for the signal propagation time differences brought about by the data signal lines, in some instances having a length measured in meters, the connections and also the terminal electronics, in the test arrangement illustrated in
FIG. 2
the evaluation instants of an input stage are set by a calibration circuit KAL integrated in the test unit. The input stage contains differential amplifiers which compare the received data signals with a static comparator voltage V
com
, generated by a comparator voltage generator KONP.
The disadvantage of the test arrangement according to the prior art as shown in
FIG. 2
is that it is highly susceptible to the timing jitter and to DC or DC voltage level drifts.
FIGS. 3
a
to
3
c
show the calibrateable test arrangement according to the prior art in accordance with FIG.
2
and the associated signals for elucidating the problems occurring here.
A data signal SIG
DUT
output by the circuit to be tested DUT is received with a certain signal delay as signal SIG
tester
by the input stage of the external test unit and is compared with a comparator voltage V
comp
by a differential amplifier. In the same way, the circuit to be tested DUT outputs an inverted data signal {overscore (SIG)}
DUT
, which is received as inverted data signal {overscore (sig)}
tester
by the input stage of the external tester unit and is compared with the set comparator voltage V
comp
as threshold value by a second differential amplifier.
FIG. 3
b
shows, by way of example, an alternating data sequence 101010 and the associated output data signals at the output data driver of the circuit to be tested DUT.
FIG. 3
c
shows, by way of example, how this output data output signal is received by an input stage of the external test unit on account of a DC voltage fluctuation. If the received data signal SIG
tester
is above the comparator voltage V
comp
and, at the same time, the data signal SIG
tester
inverted with respect thereto lies below the comparator voltage, the input stage outputs a logic high datum H for further data processing. Conversely, if the received data signal is lower than the comparator voltage level and, at the same time, the inverted data signal is above the comparator voltage level, the input stage of the test unit outputs a logic zero L for further data processing.
If both the received data signal and the inverted data signal lie below the comparator DC voltage level, this is interpreted as a data transmission error F. The same applies if both the received data signal and the data signal inverted with respect thereto lie above the comparator DC voltage level.
In the example illustrated in
FIG. 3
c,
the potential of the data signal levels is pulled down on account of a DC voltage drift, so that, from the instant t
2
, both the received data signal sigtester and the inverted data signal {overscore (Sig
tester
)} with respect thereto lie below the comparator DC voltage level and, consequently, a data transmission error F is identified. A test unit with a calibrateable input stage for compensating for signal propagation time differences between the data signal lines of a data signal line pair is thus highly sensitive to potential fluctuations on the signal lines, so that test errors can occur.
The test arrangement according to the prior art as illustrated in
FIG. 1
is relatively insensitive to the potential fluctuations on the data signal lines, but the signal propagation time differences between the data lines of a data line pair lead to test errors. By contrast, in the case of the test arrangement according to the prior art as illustrated in
FIG. 2
, said propagation time differences are compensated for by a calibration circuit, but this procedure leads to test errors on account of DC voltage level fluctuations on the data signal lines, as explained in connection with
FIGS. 3
a
to
3
c.
Therefore, the object of the present invention is to provide a test circuit for testing a circuit which avoids test errors on account of signal propagation time differences and, at the same time, is insensitive to potential fluctuations on the data signal li

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