Test circuit for an unprogrammed OTP memory array

Details Test circuit for an unprogrammed OTP memory array Test circuit for an unprogrammed OTP memory array

2008-12-23

2011-11-15

Le, Vu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S096000

Reexamination Certificate

active

08059479

ABSTRACT:
Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a test wordline. The bitline voltages can be sensed, thereby allowing for testing of the column decoding and sense amplifier circuits. The row test circuitry charges a test bitline to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a wordline of the OTP memory array. This test bitline voltage can be sensed, thereby allowing for testing of the row decoding and driver circuits.

REFERENCES:
patent: 5007026 (1991-04-01), Gaultier et al.
patent: 6515923 (2003-02-01), Cleeves
patent: 7136322 (2006-11-01), Brennan et al.
patent: 7298665 (2007-11-01), So et al.
patent: 7402855 (2008-07-01), Kurjanowicz
patent: 2007/0257331 (2007-11-01), Kurjanowicz et al.
Canadian Patent Application No. 2,646,220: Office Action dated Mar. 27, 2009.
International Patent Application No. PCT/CA2009/000368, International Search Report dated Jul. 10, 2009.

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