Test arrangement for assemblages of intergrated circuit blocks

Details Test arrangement for assemblages of intergrated circuit blocks Test arrangement for assemblages of intergrated circuit blocks

2006-01-17

2006-01-17

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06988230

ABSTRACT:
An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test interface in the chain. In addition, at its beginning, the chain is extended with a boundary scan compliant test interface for testing other parts of electronic device. Both the TDO contact of the last test interface in the chain as well as the TDO contact of test interface are coupled to a bypass multiplexer, thus yielding two possible routes from test data input to test data output: through the full chain or through test interface only. Consequently, electronic device can be tested or debugged as a macro device or as a collection of subdevices.

REFERENCES:
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 6073254 (2000-06-01), Whetsel
patent: 6223315 (2001-04-01), Whetsel
“Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits” by Steven F. Oakland. Proceedings of the international test conference (ITC); Oct. 2000, pp. 628-637.

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