Test apparatus, program and recording medium

Details Test apparatus, program and recording medium Test apparatus, program and recording medium

2007-11-13

2007-11-13

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000

Reexamination Certificate

active

11247988

ABSTRACT:
There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of the corresponding output pin and a slave channel provided in correspondence to a different output pin from that of the master channel to sample an output signal of the corresponding output pin, wherein the master channel has a frequency divider for generating a frequency-divided clock by dividing a source synchronous clock outputted from the device-under-test, a sampling section for sampling the corresponding output signal based on the frequency-divided clock and a distributing section for distributing the frequency-divided clock to the slave channel, and the slave channel has a sampling section for sampling the corresponding output signal based on the frequency-divided clock received from the master channel.

REFERENCES:
patent: 6452421 (2002-09-01), Saito
patent: 6813724 (2004-11-01), Saito
patent: 6820234 (2004-11-01), Deas et al.
patent: 6948098 (2005-09-01), Pillay et al.
patent: 402174417 (1990-07-01), None
patent: 2004-239754 (2004-08-01), None
patent: WO-2005/093443 (2005-10-01), None
Japanese Search Report issued in PCT/JP2006/320124 dated Dec. 18, 2006 (4 pages).
English Translation of Japanese Search Report issued in PCT/JP2006/320124 dated Dec. 18, 2006 (4 pages).

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