Test apparatus for updating a value of the bit position in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S035000

Reexamination Certificate

active

07657812

ABSTRACT:
There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits. Here, the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction.

REFERENCES:
patent: 5737512 (1998-04-01), Proudfoot et al.
patent: 7269770 (2007-09-01), Chung et al.
patent: 7437645 (2008-10-01), Fukuyama et al.
patent: 0773700 (1995-03-01), None
patent: 07073700 (1995-03-01), None
patent: 10271113 (1998-10-01), None
patent: 200040389 (2000-02-01), None
patent: 2004233355 (2004-08-01), None
patent: 2004264047 (2004-09-01), None

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