Test apparatus for semi-conductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

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365201, 371 251, G11C 702

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active

055397026

ABSTRACT:
A test apparatus for a semi-conductor memory device comprising a memory section having a plurality of memory cell arrays, the memory cell arrays receiving input data in parallel, a latch control circuit responsive to a write enable signal and an address signal for outputting a control signal for latching the input data while the input data is written into the memory section, an expected data latch circuit responsive to the control signal from the latch control circuit and a read enable signal for latching the input data while the input data is written into the memory section and outputting the resultant expected data, a clock generator for generating a clock signal in response to a test flag signal and an internal column address select signal, an expected data transfer circuit for transferring the expected data from the expected data latch circuit in response to the test enable signal and the read enable signal, a data discrimination circuit for discriminating whether output data from the memory section are the same as the expected data from the expected data transfer circuit, and an output circuit for outputting a fail signal in response to output signals from the data discrimination circuit.

REFERENCES:
patent: 4344127 (1982-08-01), McDaniel et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5148398 (1992-09-01), Kohno
"A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function", by Takashi OHSAWA et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 663-667.

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