Test apparatus and test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S738000, C714S744000, C365S201000, C324S765010, C326S016000

Reexamination Certificate

active

07631234

ABSTRACT:
The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.

REFERENCES:
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patent: 6006349 (1999-12-01), Fujisaki
patent: 6032282 (2000-02-01), Masuda et al.
patent: 6058057 (2000-05-01), Ochiai et al.
patent: 6374392 (2002-04-01), Ochiai et al.
patent: 6553529 (2003-04-01), Reichert
patent: 6574579 (2003-06-01), Watanabe
patent: 7294998 (2007-11-01), Chiba
patent: 2005/0001648 (2005-01-01), Yamamoto

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